The present invention relates to a method and device for verifying timing in a semiconductor integrated circuit.
In the prior art, timing verification for a digital circuit is performed by conducting, for example, static timing analysis (STA). The static timing analysis checks and ensures operation of a logic circuit by verifying timings for the circuit based on delay times assigned to respective elements in the circuit. As shown in FIG. 1, the timing verification includes a delay computation step (step 201) and a timing analysis step (STA) (step 202). In the delay computation, a processor retrieves parasitic information such as wiring parasitic capacitance from a file 203, a cell library from a file 204, and setup information such as correction information for delay computation results from a file 205. The processor then computes delay values for the respective elements of the logic circuit to generate a file 206 containing delay information. In the timing analysis, the processor performs the static timing analysis by computing an accumulated delay value in a path (signal transfer path) based on the delay information stored in the file 206 (i.e., the delay values computed in step 201) and design constraints stored in a file 207 to analyze the pulse width at an input terminal of a circuit such as a flip-flop circuit (FF circuit) or a memory. The processor then generates a result for the timing verification (timing report 208) of the logic circuit based on the result for the static timing analysis.
Delay times of elements are affected by variations in the processes performed to form transistor wiring on a semiconductor integrated circuit or variations in factors such as a power supply voltage and temperature. Therefore, in the step for computing delay values, the processor takes into account the coefficient of variation (OCV) for each element in the chip to compute the delay values. The static timing analysis, which uses the delay values computed in this manner, verifies whether or not the semiconductor integrated circuit functions normally even if there are variations between elements in the chip.
For example, referring to FIG. 2, a semiconductor integrated circuit includes an FF circuit 212 receiving a clock ck via a plurality of buffer circuits 211. Pulse width check is performed by checking the pulse width of the clock ck at a clock input terminal 212a of the FF circuit 212. The clock ck is delayed by the path delay caused by the plurality of buffer circuits 211 and reaches the FF circuit 212 as a clock ck1. The pulse width Width(H) of this clock ck1 is obtained by the following equation (1), which is based on a pulse width pw(H) of the clock ck and a rise delay time “rise_maxmax” and a fall delay time “fall_maxmin” of the clock ck1 at the input terminal of the buffer circuit 211 with respect to a supply source (e.g., an external input terminal) of the clock ck:Width(H)=PW(H)+fall_maxmin−rise_maxmax  (1)The rise delay time “rise_maxmax” is the delay time of the rising edge (rise delay) of the clock ck1 with respect to the rising edge of the clock ck under the worst conditions. The fall delay time “fall_maxmin” is the delay time of the falling edge (fall delay) of the clock ck1 with respect to the falling edge of the clock ck under the worst conditions.
The maximum value of the delay time is taken into account for the rise delay time “rise_maxmax” and the minimum value of the delay time is taken into account for the fall delay time “fall_maxmin” so that the variation between the delay times “rise_maxmax” and “fall_maxmin” is maximized to conduct a strict timing check. Japanese Laid-Open Patent Publication No. 2001-184372 describes a method for verifying a pulse width using an equation similar to equation (1).
When using a coefficient of variation OCVw under the worst conditions, the equation (1) is expressed as follows:Width(H)=PW(H)+fall_maxmax×OCVw−rise_maxmax  (2)The pulse width Width(H) obtained from equation (2) is compared with a specified value tPW for a subject cell (the FF circuit 212 in FIG. 2) to conduct the pulse width check.
Similarly, an L pulse width Width(L) under the worst conditions is obtained from the following equation:Width(L)=pw(L)+rise_maxmin−fall_maxmax=pw(L)+rise_maxmax×OCVw−fall_maxmaxAn H pulse width Width(H) under the best conditions is obtained from the following equation:Width(H)=pw(H)+fall_minmin−rise_minmax=pw(H)+fall_minmin−rise_minmin×OCVb An L pulse width Width(L) under the best conditions is obtained from the following equation:Width(L)=pw(L)+rise_minmin−fall_minmax=pw(L)+rise_minmin−fall_minmin×OCVb In the above equations, “minimin” represents the minimum delay under the best conditions, “minmax” represents the maximum delay under the best conditions, and “OCVb” represents a coefficient of variation under the best conditions.
Referring to FIG. 3, in another example, a semiconductor integrated circuit includes two FF circuits 222 and 223 receiving a clock ck via a plurality of buffer circuits 221. The first FF circuit 222 operates in synchronization with the rising edge of a clock ck1 transferred via the buffer circuits 221, and the second FF circuit 223 operates in synchronization with the falling edge of a clock ck2 transferred via the buffer circuits 221. A timing check is conducted to check the timing of data D at an input terminal 223a of the FF circuit 223 and the clock ck2 at an input terminal 223b of the FF circuit 223.